Get2Chip Puts Synthesis to the Test At EDA Front-To-Back
SOC Synthesis Leader Tells Users: "Dare to Compare" Results
SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 8, 2001--Get2Chip, the
system on chip (SOC) synthesis leader, has announced the continuation
of its "Dare to Compare" benchmark challenge at this year's EDA
Front-To-Back conference November 13-15.
The challenge, first launched at the 38th Design Automation
Conference (DAC) this year, allows users to pit their real-world
synthesis results against those achieved by Get2Chip's advanced
architectural and register transfer level (RTL) synthesis. All
benchmarking is done during the show and posted publicly. Anyone
interested in participating can sign up at the Get2Chip booth during
EDA Front-To-Back.
The popularity of these challenges led Get2Chip to formalize the
program for synthesis users, resulting in the recently announced
Jumpstart Program. The Jumpstart Lab takes a user's design and
re-synthesizes it with Get2Chip's tools, then a highly detailed
analysis is prepared, indicating time saved, quality of results, and
other performance metrics. More information is available online:
http://www.get2chip.com/index/jumpstart.asp.
"These benchmark challenges, and the more in-depth Jumpstart
program we offer SOC designers, can quickly and reliably determine if
the best tools and technology are really being applied to the problem
at hand," says Bernd U. Braune, Get2Chip's chairman, president and
chief executive officer (CEO). "For large, process-aggressive SOC
designs, we have been able to consistently demonstrate superior
quality of results (delay and area simultaneously), runtime and
capacity."
Get2Chip's entire suite of synthesis and topology-modeling
software will be on exhibit at the inaugural EDA Front-To-Back,
November 13-15, San Jose Convention Center, Booth Number 816.
About Get2Chip
Get2Chip, Inc., is a leading supplier of software products that
enable the design of the world's most complex integrated circuits,
primarily found in the communications, wireless, computer, and
consumer product markets. It was launched in 2000 by semiconductor
veterans and chip design tool experts from Cadence Design Systems,
Inc. (NYSE: CDN - news), LSI Logic Corporation (NYSE: LSI - news), Mentor Graphics
Corporation (Nasdaq: MENT - news), Synopsys (Nasdaq: SNPS - news) and VLSI
Technology -- now part of Philips Semiconductors (NYSE: PHG, AEX:
PHI). Its breakthrough front-end tool suite, VOLARE(TM), provides
fully integrated, multi-level synthesis that offers the flexibility to
do chip design at the architectural, register transfer (RTL) or gate
level. VOLARE has been developed for complex SOC designs in ultra-deep
submicron silicon technology. Its TOPOMO(TM)product integrates and
automates block partitioning, block placement, global routing and
synthesis into one front-end integrated circuit (IC) design tool.
Get2Chip is privately held and has development centers in San Jose,
Calif., and Munich, Germany. Corporate headquarters: 2107 North First
Street, Suite 350, San Jose, Calif. 95131. Telephone: (408) 501-9600.
Facsimile: (408) 501-9610. Email: info@get2chip.com. Web Site:
http://www.get2chip.com.
Get2Chip, VOLARE and TOPOMO are trademarks of Get2Chip. Get2Chip
acknowledges trademarks or registered trademarks of other
organizations for their respective products and services.
Contact:
Public Relations for Get2Chip
Nanette Collins
(617) 437-1822
nanette@nvc.com
